1. Field
This disclosure relates generally to memories, and more specifically, to a system for error detection and/or correction for memories.
2. Related Art
Traditional cache memories can typically detect only a single fault per byte, assuming they have byte parity. In such cache memories, if two bits change their value in a single byte, then no fault may be detected. In systems where higher levels of fault tolerance is necessary, the hamming distance of the code used to correct errors may need to be increased to four. The increased hamming distance, however, makes such cache memory systems complicated. In addition, complicated error correction and detection may also lower the performance of the cache memory.
Certain users of cache memories may want to incur the penalty associated with lower performance as long as they have a more robust cache memory. Other users of cache memories, however, may not care about the robustness of the cache memory and may not like the lower performance associated with the cache memory. Accordingly, there is a need for a configurable cache memory that can satisfy both types of users while maintaining a high level of performance and robustness.